View AD5254BRU10-RL7_1787498.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

quad 64-/256-position i 2 c nonvolatile memory digital potentiometers ad5253/ad5254 rev. 0 in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features ad52 53: qua d 64-position resolution ad52 54: qua d 256-position re solution 1 k?, 10 k?, 50 k?, 100 k? nonvolatile me mory 1 stores wiper settings wi th write protection power-on refreshed to eemem settings in 3 0 0 s typ eemem rewrite time = 540 s t y p resistance tole rance stored in nonvolatile me mory 12 extra b y tes i n eemem for us er-define d info rmation i 2 c? compatibl e serial interfac e direct read/write accesses of rdac 2 and eeme m registers predefine d line ar increment/decrement commands predefine d 6 db step change commands synchronous or asynchronous quad channel update wiper setting r eadback 4 mhz ban d wi dth1 k? vers ion single supply 2 . 7 v to 5. 5 v dual supply 2 .25 v to 2.75 v 2 sla v e a ddress decoding bits allow operation of 4 de vices 100-y ear t y pical dat a retenti o n, t a = 5 5 c operating temperature: C4 0 c to +85 c applic ati o ns mechanical pot e ntiometer replacement low resolution dac replacem ent rgb led backlight control white led brig htness adjustm e nt rf base station power amp bias control programmable gain and offse t control programmable attenuators programmable voltage-to-cur rent conversion programmable power supply programmable filters sensor calibrations general description the ad5253/ad5254 a r e q u ad c h a n n e l , i 2 c, no n v ol a t ile m e m- o r y , dig i tal l y co n t r o l l ed p o t e n t io m e t e rs wi th 64 /256 p o si tio n s, r e s p ecti v e l y . t h e s e d e v i ce s pe rf o r m th e sa m e e l ectr o n i c a d j u s t - me n t f u nc t i ons a s m e ch an i c a l p o te n t i o me te rs , t r i m me rs , a n d va r i a b le r e sis t o r s. the ad5253/ad5254 s v e rs a t il e p r og ra mma b i l i ty al lo ws m u l t i- ple m o de s o f o p era t io n, i n cl u d i n g r e ad/ w r i te ac ces s es i n t h e r d a c a n d eemem r e gi s t e r s , i n cr em en t / d e cr e m en t o f re s i st anc e , re s i st anc e ch ange s i n 6 d b s c a l e s , w i p e r s e t t i n g r e ad b a ck, an d e x t r a eemem fo r st o r in g us er -d ef in e d info r m a- ti o n , s u c h a s m e m o r y da ta f o r o t h e r co m p o n en ts, loo k - u p ta b l e , o r sy st em ide n t i f i ca t i on info r m a t io n . func tio n a l block di agram rdac0 regis- ter rdac1 regis- ter rdac2 regis- ter rdac3 regis- ter rdac0 rdac1 rdac2 rdac3 data control command decode logic address decode logic control logic ad5253/ad5254 i 2 c serial interface v dd a0 w0 b0 a1 w1 b1 a2 w2 b2 a3 w3 b3 v ss dgnd scl sda ad0 ad1 wp 03824-0-001 eemem power-on refresh r ab tol rdac eemem fi g u r e 1 . the ad5253/ad5254 al lo w the h o s t i 2 c co n t rol l ers t o wr i t e an y o f th e 64-/256 -st e p wi p e r s e t t ings in the rd a c r e g i s t ers an d s t o r e t h em i n t h e eemem. on c e t h e s e t t in gs a r e s t o r e d , t h e y a r e re store d a u tom a t i c a l l y to t h e r d a c re g i ste r s a t s y ste m p o we r - o n ; th e se t t i n g s c a n al so be r e s t o r ed d y n a m i c a ll y . the ad5253/ad5254 p r o v ide addi tio n al in cr em en t, decr em en t, +6 db step change, a nd C6 db step cha n ge i n sy n c hr on o u s o r asy n chr o n o us cha n n e l up da te m o de s. t h e i n crem e n t and de cr em e n t f u n c t i o n s al lo w s t ep wis e li ne a r ad j u s t men t s, w h i l e 6 db s t ep c h ang e s a r e eq ui valen t t o do ub lin g or hal v in g t h e rd a c wi p e r s e t t ing. th es e f u nc t i o n s a r e us ef u l fo r s t e e p-s l o p e n o n l ine a r ad j u st m e n t a p plic a t i o n s such as w h i t e led b r ig h t n e ss a nd a u dio vol u m e con t r o l. the ad5253/ad5254 ha v e a p a t e n t e d r e sis t ance t o lera n c e s t o r i n g fun c ti o n th a t allo w s th e use r t o a c ce s s th e eemem a n d ob t a i n t h e ab s o lute e n d - to - e nd re s i st anc e v a lu e s of t h e r d a c s fo r p r e c isio n a pplica t ion s . the ad5253/ad5254 a r e a v ail a b l e in t sso p - 20 p a c k a g es in 1 k?, 10 k?, 50 k?, a nd 100 k? o p tio n s. al l p a r t s a r e gua r a n te e d t o op era t e o v er t h e C40c t o +85c ext e n d e d ind u s t r i al t e m p era t ur e ra n g e . 1 the terms nonvol atil e memory and eem em are use d inte rchange a bl y. 2 the te rms d i gital p o te ntio m e t e r and r d a c are us ed inte rchange a bl y.
ad5253/ad5254 rev. 0 | page 2 of 28 table of contents electrical characteristics ................................................................. 3 1 k? version .................................................................................. 3 10 k?, 50 k?, 100 k? versions ................................................... 5 interface timing characteristics (all parts) ............................. 7 absolute maximum ratings ............................................................ 8 esd caution .................................................................................. 8 pin configuration and functional descriptions .......................... 9 typical performance characteristics ........................................... 10 i 2 c interface ..................................................................................... 14 i 2 c interface general description ............................................ 14 i 2 c interface detail description ............................................... 15 i 2 c compatible 2-wire serial bus ............................................ 19 theory of operation ...................................................................... 20 linear increment and decrement commands ...................... 20 6 db adjustments (doubling/halving wiper setting) ........ 20 digital input/output configuration ........................................ 21 multiple devices on one bus .................................................. 21 terminal voltage operation range ......................................... 22 power-up and power-down sequences .................................. 22 layout and power supply biasing ............................................ 22 digital potentiometer operation ............................................. 23 programmable rheostat operation ......................................... 23 programmable potentiometer operation ............................... 24 applications ..................................................................................... 25 rgb led lcd backlight controller ....................................... 25 outline dimensions ....................................................................... 27 ordering guide .......................................................................... 27 revision history revision 0: initial version
ad5253/ad5254 rev. 0 | page 3 of 28 electrical characteristics 1 k? version v dd = +3 v 10% or +5 v 10%, v ss = 0 v or v dd /v ss = 2.5 v 10%, v a = +v dd , v b = 0 v, C40c < t a < +85c, unless otherwise noted. table 1. parameter symbol conditions min typ 1 max unit dc characteristicsrheostat mode resolution n ad5253/ad5254 6/8 bits resistor differential nonlinearity 2 r-dnl r wb , r wa = nc, v dd = 5.5v, ad5253 C0.5 0.2 +0.5 lsb r wb , r wa = nc, v dd = 5.5v, ad5254 C1 0.25 +1 lsb r wb , r wa = nc, v dd = 2.7v, ad5253 C0.75 0.3 +0.75 lsb r wb , r wa = nc, v dd = 2.7v, ad5254 C1.5 0.3 +1.5 lsb resistor nonlinearity 2 r-inl r wb , r wa = nc, v dd = 5.5v, ad5253 C0.5 0.2 +0.5 lsb r wb , r wa = nc, v dd = 5.5v, ad5254 C2 0.5 +2 lsb r wb , r wa = nc, v dd = 2.7v, ad5253 C1 +2.5 +4 lsb r wb , r wa = nc, v dd = 2.7v, ad5254 C2 +9 +14 lsb nominal resistor tolerance ?r ab /r ab t a = 25c C30 +30 % resistance temperature coefficient (?r ab /r ab ) 10 6 /?t 650 ppm/c wiper resistance r w i w = 1 v/r, v dd = 5 v 75 130 ? i w = 1 v/r, v dd = 3 v 200 300 ? channel resistance matching ?r ab1 /?r ab2 0.15 % dc characteristicspotentiometer divider mode differential nonlinearity 3 dnl ad5253 C0.5 0.1 +0.5 lsb ad5254 C1 0.25 +1 lsb integral nonlinearity 3 inl ad5253 C0.5 0.2 +0.5 lsb ad5254 C2 0.5 +2 lsb voltage divider temperature coefficient (?v w /v w ) 10 6 /?t code = half scale 25 ppm/c full-scale error v wfse code = full scale, v dd = 5.5 v, ad5253 C5 C3 0 lsb code = full scale, v dd = 5.5 v, ad5254 C16 C11 0 lsb code = full scale, v dd = 2.7 v, ad5253 C6 C4 0 lsb code = full scale, v dd = 2.7 v, ad5254 C23 C16 0 lsb zero-scale error v wzse code = zero scale, v dd = 5.5 v, ad5253 0 3 5 lsb code = zero scale, v dd = 5.5 v, ad5254 0 11 16 lsb code = zero scale, v dd = 2.7 v, ad5253 0 4 6 lsb code = zero scale, v dd = 2.7 v, ad5254 0 15 20 lsb resistor terminals voltage range 4 v a , v b , v w v ss v dd v capacitance 5 ax, bx c a , c b f = 1 khz, measured to gnd, code = half scale 85 pf capacitance 5 wx c w f = 1 khz, measured to gnd, code = half scale 95 pf common-mode leakage current i cm v a = v b = v dd /2 0.01 1 a digital inputs and outputs input logic high v ih v dd = 5 v, v ss = 0 v 2.4 v v dd /v ss = +2.7 v/0 v or v dd /v ss = 2.5 v 2.1 v input logic low v il v dd =5 v, v ss = 0 v 0.8 v v dd /v ss = +2.7 v/0 v or v dd /v ss = 2.5 v 0.6 v output logic high (sda) v oh r pull-up = 2.2 k? to v dd = 5 v, v ss = 0 v 4.9 v output logic low (sda) v ol r pull-up = 2.2 k? to v dd =5 v, v ss = 0 v 0.4 v wp leakage current i wp wp = v dd 5 a
ad5253/ad5254 rev. 0 | page 4 of 28 parameter symbol conditions min typ 1 max unit digital inputs and outputs (continued) a0 leakage current i a0 a0 = gnd 3 a input leakage current (other than wp and a0) i i v in = 0 v or v dd 1 a input capacitance 5 c i 5 pf power supplies single-supply power range v dd v ss = 0 v 2.7 5.5 v dual-supply power range v dd /v ss 2.25 2.75 v positive supply current i dd v ih = v dd or v il = gnd 5 15 a negative supply current i ss v ih = v dd or v il = gnd, v dd = +2.5 v, v ss = C2.5 v C5 C15 a eemem data storing mode current i dd_store v ih = v dd or v il = gnd 35 ma eemem data restoring mode current 6 i dd_restore v ih = v dd or v il = gnd 2.5 ma power dissipation 7 p diss v ih = v dd = 5 v or v il = gnd 0.075 mw power supply sensitivity pss ?v dd = 5 v 10% ?0.025 0.01 0.025 %/% ?v dd = 3 v 10% C0.04 0.02 0.04 %/% dynamic characteristics 5 , 8 bandwidth C3 db bw r ab = 1 k? 4 mhz total harmonic distortion thd v a =1 v rms, v b = 0 v, f = 1 khz 0.05 % v w settling time t s v a = v dd , v b = 0 v 0.2 s resistor noise voltage e n_wb r wb = 500 ?, f = 1 khz. thermal noise only. 3 nv/ hz digital crosstalk c t v a = v dd , v b = 0 v, measure v w with adjacent rdac making full-scale change C80 db analog coupling c at signal input at a0 and measure the output at w1, f = 1 khz C72 db
ad5253/ad5254 rev. 0 | page 5 of 28 10 k?, 50 k?, 100 k? versions v dd = +3 v 10% or +5 v 10%, v ss = 0 v or v dd /v ss = 2.5 v 10%, v a = +v dd , v b = 0 v, C40c < t a < +85c, unless otherwise noted. table 2. parameter symbol conditions min typ 1 max unit dc characteristicsrheostat mode resolution n ad5253/ad5254 6/8 bits resistor differential nonlinearity 2 r-dnl r wb , r wa = nc, ad5253 ?0.75 0.1 +0.75 lsb r wb , r wa = nc, ad5254 ?1 0.25 +1 lsb resistor nonlinearity 2 r-inl r wb , r wa = nc, ad5253 ?0.75 0.25 +0.75 lsb r wb , r wa = nc, ad5254 ?2.5 1 +2.5 lsb nominal resistor tolerance ?r ab /r ab t a = 25c ?20 +20 % resistance temperature coefficient (?r ab /r ab ) 10 6 /?t 650 ppm/c wiper resistance r w i w = 1 v/r, v dd = 5 v 75 130 ? i w = 1 v/r, v dd = 3 v 200 300 ? channel resistance matching ?r ab1 /?r ab2 r ab = 10 k?, 50 k? 0.15 % r ab = 100 k? 0.05 % dc characteristicspotentiometer divider mode differential nonlinearity 3 dnl ad5253 ?0.5 0.1 +0.5 lsb ad5254 ?1 0.3 +1 lsb integral nonlinearity 3 inl ad5253 ?0.5 0.15 +0.5 lsb ad5254 ?1.5 0.5 +1.5 lsb voltage divider temperature coefficient (?v w /v w ) 10 6 /?t code = half scale 15 ppm/c full-scale error v wfse code = full scale, ad5253 ?1 ?0.3 0 lsb code = full scale, ad5254 ?3 ?1 0 lsb zero-scale error v wzse code = zero scale, ad5253 0 0.3 1 lsb code = zero scale, ad5254 0 1.2 3 lsb resistor terminals voltage range 4 v a , v b , v w v ss v dd v capacitance 5 ax, bx c a , c b f = 1 khz, measured to gnd, code = half scale 85 pf capacitance 5 wx c w f = 1 khz, measured to gnd, code = half scale 95 pf common-mode leakage current 6 i cm v a = v b = v dd /2 0.01 1 a digital inputs and outputs input logic high v ih v dd = 5 v, v ss = 0 v 2.4 v v dd /v ss = +2.7 v/0 v or v dd /v ss = 2.5 v 2.1 v input logic low v il v dd = 5 v, v ss = 0 v 0.8 v v dd /v ss = +2.7 v/0 v or v dd /v ss = 2.5 v 0.6 v output logic high (sda) v oh r pull-up = 2.2 k? to v dd = 5 v, v ss = 0 v 4.9 v output logic low (sda) v ol r pull-up = 2.2 k? to v dd = 5 v, v ss = 0 v 0.4 v wp leakage current i wp wp = v dd 5 a a0 leakage current i a0 a0 = gnd 3 a input leakage current (other than wp and a0) i i v in = 0 v or v dd 1 a input capacitance 5 c i 5 pf power supplies single-supply power range v dd v ss = 0 v 2.7 5.5 v dual-supply power range v dd /v ss 2.25 2.75 v positive supply current i dd v ih = v dd or v il = gnd 5 15 a
ad5253/ad5254 rev. 0 | page 6 of 28 parameter symbol conditions min typ 1 max unit power supplies (continued) negative supply current i ss v ih = v dd or v il = gnd, v dd = +2.5 v, v ss = ?2.5 v ?5 ?15 a eemem data storing mode current i dd_store v ih = v dd or v il = gnd, t a = 0c to 85c 35 ma eemem data restoring mode current 6 i dd_restore v ih = v dd or v il = gnd, t a = 0c to 85c 2.5 ma power dissipation 7 p diss v ih = v dd = 5 v or v il = gnd 0.075 mw power supply sensitivity pss ?v dd = 5 v 10% ?0.005 +0.002 +0.005 %/% ?v dd = 3 v 10% ?0.01 +0.002 +0.01 %/% dynamic characteristics 5 , 8 C3 db bandwidth bw r ab = 10 k?/50 k?/100 k? 400/80/40 khz total harmonic distortion thdw v a = 1 vrms, v b = 0 v, f = 1 khz 0.05 % v w settling time t s v a = v dd , v b = 0 v, r ab = 10 k?/50 k?/100 k? 1.5/7/14 s resistor noise voltage e n_wb r ab = 10 k?/50 k?/100 k?, code = midscale, f = 1 khz. thermal noise only. 9/20/29 nv/ hz digital crosstalk c t v a = v dd , v b = 0 v, measure v w with adjacent rdac making full scale change ?80 db analog coupling c at signal input at a0 and measure output at w1, f = 1 khz ?72 db
ad5253/ad5254 rev. 0 | page 7 of 28 interface timing characteristics (all parts) guaranteed by design, not subject to production test. see figure 23 for location of measured values. all input control voltages are specified with t r = t f = 2.5 ns (10% to 90% of 3 v) and timed from a voltage level of 1.5 v. switching characteristics are measured using both v dd = 3 v and 5 v. when the part is not in operation, the sda and scl pins should be pulled high. when these pins are pulled low, the i 2 c interface at these pins conducts current of about 0.8 ma at v dd = 5.5 v and 0.2 ma at v dd = 2.7 v. table 3. parameter symbol conditions min typ 1 max unit scl clock frequency f scl 400 khz t buf bus free time between stop and start t 1 1.3 s t hd;sta hold time (repeated start) t 2 after this period, the first clock pulse is generated 0.6 s t low low period of scl clock t 3 1.3 s t high high period of scl clock t 4 0.6 s t su;sta setup time for start condition t 5 0.6 s t hd;dat data hold time t 6 0 0.9 s t su;dat data setup time t 7 100 ns t f fall time of both sda and scl signals t 8 300 ns t r rise time of both sda and scl signals t 9 300 ns t su;sto setup time for stop condition t 10 0.6 s eemem data storing time t eemem_store 26 ms eemem data restoring time at power on 9 t eemem_restore1 v dd rise time dependent. measure without decoupling capacitors at v dd and v ss . 300 s eemem data restoring time upon restore command or reset operation 9 t eemem_restore2 v dd = 5 v 300 s eemem data rewritable time 10 t eemem_rewrite 540 s flash/ee memory reliability endurance 11 100 kcycles data retention 12 100 years 1 typical values represent av erage readings at 25c and v dd = 5 v. 2 resistor position nonlinearity error (r-inl) is the deviatio n from an ideal value measured be tween the maximum resistance and the minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic, except r-dnl of ad5254 1 k? version at v dd = 2.7v, i w = v dd /r for both v dd = 3 v or v dd = 5 v. 3 inl and dnl are measured at v w with the rdac configured as a potentiometer divide r similar to a voltage ou tput d/a converter. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 4 resistor terminals a, b, and w have no limitations on polari ty with respect to each other. 5 guaranteed by design and not subject to production test. 6 cmd 0 nop should be activated after cmd 1 in order to minimize i dd_restore current consumption. 7 p diss is calculated from (i dd v dd = 5 v). 8 all dynamic characteristics use v dd = 5 v. 9 during power-up, all outputs preset to midscale before restor ing eemem contents. rdac0 has the shortest whereas rdac3 has the longest eemem restore time. 10 delay time after power-on or reset before new eemem data to be written. 11 endurance is qualified to 100,000 cycles per jedec std. 22 method a117, and is measured at C40c, +25c, and +85c; typical en durance at +25c is 700,000 cycles. 12 retention lifetime equivalent at junction temperature (t j ) = 55c per jedec std. 22, method a117 . retention lifetime ba sed on an activation energy of 0.6ev derates with junction temperature.
ad5253/ad5254 rev. 0 | page 8 of 2 8 absolute maximum ra tings table 4. t a = 2 5 c, u n les s ot herwi s e not e d p a r a m e t e r r a t i n g v dd to gnd ?0.3 v, +7 v v ss to gnd +0.3 v, ?7 v v dd to v ss 7 v v a , v b , v w to gn d v ss , v dd maximum current i wb , i wa pulsed 20 ma i wb continuous (r wb 1 k?, a open) 1 5 ma i wa continuous (r wa 1 k?, b op en) 1 5 ma i ab continuous ( r ab = 1 k?/10 k?/50 k?/100 k?) 1 5 ma/500 a/100 a/50 a digital inputs and output voltage to gnd 0 v, 7 v operating temperature range ?40c to +85c maximum junction temperature (t j max ) 1 5 0 c storage temperature ?65c to +150c lead temperature (soldering, 10 sec) 300c vapor phase (60 sec) 215c infrared (15 sec) 220c tssop-20 ther mal resistance 2 ja 143c/w s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y ca us e p e r m an e n t da ma g e t o t h e de vice . this is a s t r e s s ra t i n g o n ly ; f u nc t i on a l o p e r a t i o n of t h e d e v i c e a t t h e s e or a n y ot h e r c o n d i t i ons ab ove t h o s e l i ste d i n t h e op e r a t i o n a l s e c t i o ns of t h i s sp e c if ica t ion is n o t im plie d . e x p o sur e to a b s o l u te m a x i m u m r a t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vi ce r e liab i l i t y . 1 maximum terminal current is boun ded by the maximum applied v o ltage acro ss any two o f the a, b, and w terminals at a given resi s t ance, the maximum current h a n dli n g of t h e swi t ch es, a n d t h e m a x i m um power di s s i p a t i o n of t h e pa cka g e. v dd = 5v . 2 pa cka g e pow e r di s s i p a t i o n = (t jm ax ? t a )/ ja . esd c a ution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
ad5253/ad5254 rev. 0 | page 9 of 2 8 pin conf igura t ion and fu nctional descri ptions ad5253/ ad5254 top view (not to scale) w0 1 b0 2 a0 3 ad0 4 5 w1 1 b1 2 a1 3 sd a 4 v ss 5 v dd w3 b3 a3 ad1 10 9 8 7 6 dgnd scl w2 b2 a2 10 9 8 7 6 03842-0-002 wp f i g u re 2. a d 52 53 /a d52 5 4 pin conf ig u r at i o n table 5. ad52 53/ad5254 pi n fu nction des c riptions pin o . m n e m o n i c d e s c r i p t i o n 1 w0 wiper terminal of rdac0. v ss v w0 v dd . 2 b0 b terminal of rdac0. v ss v b0 v dd . 3 a0 a terminal of rdac0. v ss v a0 v dd . 4 a d 0 i 2 c device addr ess 0. ad0 and ad1 allow four ad5253/ad525 4s to be addressed. 5 wp write protect, active low. v wp v dd + 0.3 v. 6 w1 wiper terminal of rdac1. v ss v w1 v dd . 7 b1 b terminal of rdac1. v ss v b1 v dd . 8 a1 a terminal of rdac1. v ss v a1 v dd . 9 s d a serial data inpu t/ output pin. sh ifts in one bit at a time on positi ve cloc k cl k edges. msb loaded first. open-drai n m o sfet requires pull-up resi sto r. 1 0 v ss negative supply. connect to 0 v for single su pply or C2.7 v for dual supply, where v dd C v ss +5.5 v. if v ss is used, rather than grounded, in d u al supply, v ss must be able to sink 3 5 ma fo r 26 ms when storing data to eeme m . 11 a2 a terminal of rdac2. v ss v a2 v dd . 12 b2 b terminal of rdac2. v ss v b2 v dd . 13 w2 wiper terminal of rdac2. v ss v w2 v dd . 1 4 s c l serial input register clock pin. s h ifts in one bit a t a time on posit ive cloc k edges. v scl ( v dd + 0.3 v) . pull-up resistor is recomme nded for scl to ens u re minimum power. 15 dgnd digital ground. connect to system anal og ground at a single p o int. 1 6 a d 1 i 2 c device addr ess 1. ad0 and ad1 allow four ad5253/ad525 4s to be addressed. 17 a3 a terminal of rdac3. v ss v a3 v dd . 18 b3 b terminal of rdac3. v ss v b3 v dd . 19 w3 w terminal of rdac3. v ss v w3 v dd . 2 0 v dd positive power s u pply pin. connect +2.7 v to +5 v for single sup p ly or 2.7 v for d u al supply, wh ere v dd C v ss 5. 5 v. v dd must be able to source 35 ma fo r 26 ms when storing data to eeme m .
ad5253/ad5254 rev. 0 | page 10 of 28 typical performance characteristics r-inl (lsb) code (decimal) 03824-0-015 t a = ?40c, +25c, +85c, +125c ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 32 64 96 128 160 192 224 256 figure 3. r-inl vs. code rdnl (lsb) code (decimal) 03824-0-016 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 32 64 96 128 160 192 224 256 t a = ?40c, +25c, +85c, +125c figure 4. r-dnl vs. code inl (lsb) code (decimal) 03824-0-017 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 32 64 96 128 160 192 224 256 t a = ?40c, +25c, +85c, +125c figure 5. inl vs. code inl (lsb) code (decimal) 03824-0-018 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 32 64 96 128 160 192 224 256 t a = ?40c, +25c, +85c, +125c figure 6. dnl vs. code supply current ( a) temperature ( c) 03824-0-019 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 ?40 ?20 0 20 40 60 80 100 120 i dd @ v dd = +5.5v i dd @ v dd = +2.7v i ss @ v dd = +2.7v, v ss = ?2.7v figure 7. supply current vs. temperature digital input voltage (v) 03824-0-020 0.0001 0.01 0.001 0.1 1 10 0123456 v dd = 5.5v v dd = 2.7v i dd (ma) figure 8. supply current vs. digital input voltage. t a = 25c
ad5253/ad5254 rev. 0 | page 11 of 28 r wb ( ? ) v bias (v) 03824-0-021 20 0 40 60 80 100 120 140 160 200 240 180 220 1 0 23456 v dd = 2.7v t a = 25 c v dd = 5.5v t a = 25 c data = 0x00 f i gure 9. wipe r r e s i s t anc e v s . v bias temperature ( c) 03824-0-022 ?6 ?4 ?2 0 2 4 6 ? 4 0 ? 20 0 2 0 4 0 6 0 8 0 100 120 ? r wb (%) f i gure 1 0 . change o f r ab v s . t e mper atur e code (decimal) 03824-0-023 0 50 60 70 20 10 30 40 80 90 0 3 2 6 4 9 6 128 160 192 224 256 rheostat mode tempco (ppm/ c) v dd = 5v t a = ? 40 c/+85 c v a = v dd v b = 0v f i gure 11. r h e o stat mode t e mpco (?r wb /r wb )/?t 10 6 vs . c o de code (decimal) 03824-0-024 0 20 25 10 5 15 30 0 3 2 6 4 9 6 128 160 192 224 256 p o te ntiome te r mode tempco (ppm/ c) v dd = 5v t a = ? 40 c/+85 c v a = v dd v b = 0v f i gure 1 2 . p o tentiom e ter m o de t e m p co (? v wb /v wb )/?t 10 6 vs . c o de ?6 0 ?4 8 ?2 4 ?1 2 0 ?3 6 ?5 4 ?3 0 ?1 8 ?6 ?4 2 gain ( d b) 1k 10k 10 100 100k 1m 10m frequency (hz) 03824-0-025 0xff 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 0x00 f i gure 13. g a in vs. f r equ e nc y vs. c o d e , r ab = 1 k? , t a = 25 c ?60 ?48 ?24 ?12 0 ?36 ?54 ?30 ?18 ?6 ?42 gain ( d b) 1k 10k 10 100 100k 1m 10m frequency (hz) 03824-0-026 0xff 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 0x00 f i gure 14. g a in vs. f r equ e nc y vs. c o d e , r ab = 10 k? , t a = 25 c
ad5253/ad5254 rev. 0 | page 12 of 28 ?6 0 ?4 8 ?2 4 ?1 2 0 ?3 6 ?5 4 ?3 0 ?1 8 ?6 ?4 2 gain ( d b) 1k 10k 10 100 100k 1m 10m frequency (hz) 03824-0-027 0xff 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 0x00 f i gure 15. g a in vs. f r equ e nc y vs. c o d e , r ab = 50 k? , t a = 25 c ?6 0 ?4 8 ?2 4 ?1 2 0 ?3 6 ?5 4 ?3 0 ?1 8 ?6 ?4 2 gain ( d b) 1k 10k 10 100 100k 1m 10m frequency (hz) 03824-0-028 0xff 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 0x00 f i gure 16. g a in vs. f r equ e nc y vs. c o d e , r ab = 10 0 k? , t a = 25 c ? r ab ( ? ) code (decimal) 03824-0-029 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 100 0 3 2 6 4 9 6 128 160 192 224 256 100k ? 10k ? 50k ? v dd = 5.5v 1k ? f i g u re 17. ?r ab vs. c o de , t a = 2 5 c clock frequency (hz) 03824-0-030 0 0.6 0.4 0.2 0.8 1.0 1.2 1 100 10 1k 10k 100k 1m 10m v dd = 2.7v t a = 25c v dd = 5.5v i dd (ma) f i gure 1 8 . sup p l y current vs . di gi tal input cl ock f r equenc y 03824-0-031 digital feedthrough clk vdd = 5v v w mid-scale transition 7fh 80h f i g u re 19. cl ock f e edt h roug h and m i ds c a l e t r ans i t i on g lit ch 03824-0-046 vwb0 (0xff stored in eemem) vwb3 (0xff stored in eemem) vdd = va0 = va3 = 3.3v gnd = vb0 = vb3 midscale preset restore rdac0 setting to 0xff restore rdac3 setting to 0xff vdd (no de- coupling caps) midscale preset f i g u re 20. t eemem_ r es t o r e of r d a c 0 and r d a c 3
ad5253/ad5254 rev. 0 | page 13 of 28 code (decimal) 03824-0-033 0 3 2 1 4 5 6 0 8 16 24 32 40 48 56 64 the o re tical i wb _ m a x (ma) r ab = 1k ? v a = v b = open t a =2 5 c r ab = 10k ? r ab = 50k ? r ab = 100k ? f i g u re 21. i wb_max v s . code (a d5 25 3) code (decimal) 03824-0-034 0 3 2 1 4 5 6 0 3 2 6 4 9 6 128 160 192 224 256 the o re tical i wb _ m a x (ma) r ab = 1k ? v a = v b = open t a =2 5 c r ab = 10k ? r ab = 50k ? r ab = 100k ? f i g u re 22. i wb_max v s . code (a d5 25 4)
ad5253/ad5254 rev. 0 | page 14 of 28 i 2 c interf ace t 1 scl sda ps p 0 3842-0-003 t 3 t 2 t 8 t 9 t 8 t 9 t 4 t 5 t 7 t 6 t 10 f i g u re 23. i 2 c int e r f ac e ti m i ng d i ag r a m i 2 c interf a c e gener a l description fr o m ma s t e r t o s l av e f r o m sla ve t o m a st er s = s t a r t c o n d i t io n. p = s t o p c o n d i t io n. a = a c k n o w le dge (s d a l o w). a = n o t a c k n o w ledg e (s d a h i g h ). r/ w = read enable a t h i g h ; w r i t e ena b le a t l o w . r/w a/a s slave address (7-bit) a 0 write a instructions (8-bit) data transferred (n bytes + acknowledge) data (8-bit) p 03842-0-004 f i g u re 24. i 2 cm a ster writ ing d a t a to s l ave r/w a s slave address (7-bit) 1 read data transferred (n bytes + acknowledge) data (8-bit) data (8-bit) p 03842-0-005 a a f i g u re 25. i 2 cm a s t er r e ading d a t a f r o m sl ave r/w r/w s slave address (7-bit) read or write (n bytes + acknowledge) slave address data a s 03842-0-006 repeated start read or write direction of transfer may change at this point a a/a (n bytes + acknowledge) data p a/a f i g u re 26. i 2 c c o mbin ed w r it e/read
ad5253/ad5254 rev. 0 | page 15 of 28 i 2 c interf a c e de t a il descripti o n fr o m ma s t e r t o s l av e f r o m sla ve t o m a st er s = s t a r t c o n d i t io n. p = s t o p c o n d i t io n. a = a c k n o w le dge (s d a l o w). a = n o t a c k n o w ledg e (s d a h i g h ). ad1, ad0 = i 2 c d e vic e a d dr es s bi ts. m u s t ma t c h wi t h t h e log i c s t a t es a t p i n s ad1, ad0 . r/ w = r e a d en a b le b i t , logi c h i g h /w ri t e en a b l e b i t , logi c lo w . cmd/ reg = c o m m a n d en a b l e b i t , logi c h i g h /re g i s t e r a c c e s s b i t , logi c lo w . ee/ rd a c = e e m e m r e gi s t e r , logi c h i gh/ r d a c r e gi s t e r , logi c lo w . a 4 , a 3 , a 2 , a 1 , a 0 = rd a c /ee m em reg i st er a ddr es s e s. 0 write 03842-0-007 s 0 1 0 1 1 a d 1 a d 0 0 a a 4 a 3 a 2 a 1 a 0 a p data 0 (1 byte + acknowledge) slave address instructions and address cmd/ reg ee/ rdac 0 reg a/ a f i g u re 27. sing le writ e m o d e 0 write 03842-0-008 s 0 1 0 1 1 a d 1 a d 0 0 a a 4 a 3 a 2 a 1 a 0 p a a rdac_n data rdac_n + 1 data 0 (n byte + acknowledge) slave address instructions and address cmd/ reg ee/ rdac 0 reg a/ a f i g u re 28. cons ecu t i ve w r ite m o d e tab l e 6. add r esses for writin g data by te con t en ts to rdac registers (r/ w = 0, cm d/ reg = 0, ee/ rdac = 0) a 4 a 3 a 2 a 1 a 0 r d a c data b y te desc riptio n 0 0 0 0 0 rdac0 6-/8-bit wiper se tting (2 msbs of ad5253 are x) 0 0 0 0 1 rdac1 6-/8-bit wiper se tting (2 msbs of ad5253 are x) 0 0 0 1 0 rdac2 6-/8-bit wiper se tting (2 msbs of ad5253 are x) 0 0 0 1 1 rdac3 6-/8-bit wiper se tting (2 msbs of ad5253 are x) 0 0 1 0 0 r e s e r v e d : : : : : 0 1 1 1 1 r e s e r v e d
ad5253/ad5254 rev. 0 | page 16 of 28 rdac/eemem write setting the wiper position requires an rdac write operation. the single write operation is shown in figure 27, and the consecutive write operation is shown in figure 28. in consecutive write operation, if the rdac is selected and the address starts at 0, the first data byte goes to rdac0, the second data byte goes to rdac1, the third data byte goes to rdac2, and the fourth data byte goes to rdac3. this operation can be continued up to eight addresses with four unused addresses; it then loops back to rdac0. if the address starts at any of the eight valid addresses, n, the data first goes to rdac_n, rdac_n + 1, and so on; it loops back to rdac0 after the eighth address. the rdac address is shown in table 6. while the rdac wiper setting is controlled by a specific rdac register, each rdac register corresponds to a specific eemem memory location, which provides nonvolatile wiper storage functionality. the addresses are shown in table 7. the single and consecutive write operations also apply to eemem write operations. there are 12 nonvolatile memory locations, eemem4 to eemem15, where users can store 12 bytes of information such as memory data for other components, look-up table, or system identification information. in a write operation to the eemem registers, the device disables the i 2 c interface during the internal write cycle. acknowledge polling, which is discussed later in the data sheet, is required to determine the completion of the write cycle. rdac/eemem read the ad5253/ad5254 provide two different rdac or eemem read operations. for example, figure 29 shows the method of reading the rdac0 to rdac3 contents without specifying the address, assuming address rdac0 was already selected from the previous operation. if rdac_n, other than address 0, is selected previously, readback starts with address n, followed by n + 1, and so on. figure 30 illustrates the random rdac or eemem read opera- tion. this operation allows users to specify which rdac or eemem register is read by first issuing a dummy write command to change the rdac address pointer, and then proceeding with the rdac read operation at the new address location. table 7. addresses for writing (storing) rdac settings and user-defined data to eemem registers (r/ w = 0, cmd/ reg = 0, ee/ rdac = 1) a4 a3 a2 a1 a0 data byte description 0 0 0 0 0 store rdac0 setting to eemem0 1 0 0 0 0 1 store rdac1 setting to eemem1 1 0 0 0 1 0 store rdac2 setting to eemem2 1 0 0 0 1 1 store rdac3 setting to eemem3 1 0 0 1 0 0 store user data to eemem4 0 0 1 0 1 store user data to eemem5 0 0 1 1 0 store user data to eemem6 0 0 1 1 1 store user data to eemem7 0 1 0 0 0 store user data to eemem8 0 1 0 0 1 store user data to eemem9 0 1 0 1 0 store user data to eemem10 0 1 0 1 1 store user data to eemem11 0 1 1 0 0 store user data to eemem12 0 1 1 0 1 store user data to eemem13 0 1 1 1 0 store user data to eemem14 0 1 1 1 1 store user data to eemem15 table 8. addresses for reading (restoring) rdac settings and user data from eemem (r/ w = 1, cmd/ reg = 0, ee/ rdac = 1) a4 a3 a2 a1 a0 data byte description 0 0 0 0 0 read rdac0 setting from eemem0 0 0 0 0 1 read rdac1 setting from eemem1 0 0 0 1 0 read rdac2 setting from eemem2 0 0 0 1 1 read rdac3 setting from eemem3 0 0 1 0 0 read user data from eemem4 0 0 1 0 1 read user data from eemem5 0 0 1 1 0 read user data from eemem6 0 0 1 1 1 read user data from eemem7 0 1 0 0 0 read user data from eemem8 0 1 0 0 1 read user data from eemem9 0 1 0 1 0 read user data from eemem10 0 1 0 1 1 read user data from eemem11 0 1 1 0 0 read user data from eemem12 0 1 1 0 1 read user data from eemem13 0 1 1 1 0 read user data from eemem14 0 1 1 1 1 read user data from eemem15 1 user can store any 64 rdac setting s for ad5253 or 256 rdac settings for ad5254, not limited to current rdac wi per setting, directly to eemem.
ad5253/ad5254 rev. 0 | page 17 of 28 1 read 03842-0-009 s 0 1 0 1 1 a d 1 a d 0 1 a p a rdac_n or eemem_n register data rdac_n + 1 or eemem_n + 1 register data slave address (n bytes + acknowledge) a f i gur e 2 9 . rd a c c u r r ent re a d . re str i c t e d t o p r e v i o usly s e l e c t ed address sto r ed in the r e g i ste r . p s slave address 0 write slave address instructional and address a 1 s 03842-0-010 repeated start 1 read a 0a (n bytes + acknowledge) rdac or eemem data a/a f i gur e 3 0 . rd a c or eemem r a ndom r e a d 0 write 03842-0-011 1 cmd s 0 1 0 1 1 a d 1 a d 0 0 a c 3 c 2 c 1 c 0 a 2 a 1 a 0 a p rdac slave address cmd/ reg f i g u re 31. r d a c q u ick com m a nd w r i t e ( d u m m y w r it e) fr o m ma s t e r t o s l av e f r o m sla ve t o m a st er s = s t a r t c o n d i t io n p = s t o p c o n d i t io n a = a c k n o w le dge (s d a l o w) a = n o t a c k n o w ledg e (s d a h i g h ) ad1, ad0 = i 2 c d e vic e a d dr es s bi ts. m u s t ma t c h wi t h t h e log i c s t a t es a t p i n s ad1, ad0 . r/ w = r e a d en a b l e b i t , logi c h i g h /w ri t e en a b l e b i t , logi c lo w cmd/ reg = c o m m a n d en a b l e b i t , logi c h i g h /re g i s t e r a c c e s s b i t , logi c lo w c3, c2, c1, c0 = c o mma nd b i ts a2, a1, a0 = r d a c /eemem reg i st er a d dr ess e s table 9. r d ac -to-eemem interface and r d ac operation quick comma nd bits (cmd/ reg = 1, a2 = 0) c 3 c 2 c 1 c 0 command des c r i p t i o n 0 0 0 0 n o p 0 0 0 1 restore eemem (a1, a0) to rd a c (a1, a0 ) 1 0 0 1 0 store rdac (a1, a0) to e e me m (a1, a0) 0 0 1 1 decrement rdac (a1, a0 ) 6 db 0 1 0 0 decrement all rdacs 6 db 0 1 0 1 decrement rdac (a1, a0 ) one step 0 1 1 0 decrement all rdacs one step 0 1 1 1 reset: restore eem em s to all rdacs 1 0 0 0 increment rdacs (a1, a0) 6 db 1 0 0 1 increment all rdacs 6 db 1 0 1 0 increment rdacs (a1, a0) one step 1 0 1 1 increment all rdacs one step 1 1 0 0 r e s e r v e d : : : : 1 1 1 1 r e s e r v e d rdac/eemem uick commands ad5253/ad52 54 f e a t ur e 12 q u ic k co mma nds t h a t facil i t a t e e a s y m a n i pu l a t i on of r d a c w i p e r s e tt i n g s a s wel l a s prov i d e r d a c - t o - e e m e m stor i n g a n d re stor i n g f u nc t i ons . t h e co mman d fo r m a t is sh o w n i n f i gur e 31, a n d t h e co mmand des c r i p t io n s a r e sh o w n i n t a b l e 9. w h en usin g a quick co mmand , issuin g a t h ir d b y t e is n o t ne e d e d b u t i s a l l o we d. t h e qu i c k c o m m a nd s r e s e t a n d store r d a c to e e m e m re qu i r e a c k n ow l e dg e p o l l i n g to de te r m i n e w h et her t h e comman d has f i ni s h e d exe c u t ing. 1 this command l e a v es the d e vice in the ee me m rea d pow e r s t ate, which cons umes power. iss u e the nop c o mmand to return the devi ce to the id le st a t e.
ad5253/ad5254 rev. 0 | page 18 of 28 table 10. a ddr ess table for r e ading toleran c e (cmd/ reg = 0, ee/ rdac = 1, a4 = 1 ) a 4 a 3 a 2 a 1 a 0 d a t a b y te desc riptio n 1 1 0 0 0 s i g n and 7-bit integer valu es of rdac0 tolerance (read only) 1 1 0 0 1 8-bit decimal value of rdac0 to lerance (read only) 1 1 0 1 0 s i g n and 7-bit integer valu es of rdac1 tolerance (read only) 1 1 0 1 1 8-bit decimal value of rdac1 to lerance (read only) 1 1 1 0 0 s i g n and 7-bit integer valu es of rdac2 tolerance (read only) 1 1 1 0 1 8-bit decimal value of rdac2 to lerance (read only) 1 1 1 1 0 s i g n and 7-bit integer valu es of rdac3 tolerance (read only) 1 1 1 1 1 8-bit decimal value of rdac3 to lerance (read only) 03842-0-012 a aa d7 d6 d5 d4 d3 d2 d1 d0 sign sign 7 bits for integer number 2 6 2 5 2 4 2 3 2 2 2 1 2 0 d7 d6 d5 d4 d3 d2 d1 d0 8 bits for decimal number 2 ?8 2 ?1 2 ?2 2 ?3 2 ?4 2 ?5 2 ?6 2 ?7 f i g u re 32. f o rm at o f sto r ed t o ler a nce i n sig n m a g n it ude f o r m at wit h b i t p o s i t i on d e s c ript io ns. u n it is %. o n ly d a t a b y tes a r e s hown. r ab tolerance stored in read-only m e mo ry ad5253/ad52 54 f e a t ur e p a t e n t ed r ab tol e r a nc e s stor age i n t h e n o n v ol a t i l e m e m o r y . the t o lera n c e o f e a ch cha nne l is st o r e d i n th e m e m o r y d u ri n g th e fa c t o r y p r od ucti o n a n d ca n be r e ad b y us ers a t an y t i me . the k n o w le dg e o f t h e s t o r e d t o lera n c e , w h ich is t h e a v era g e o f r ab o v eral l co des (f igur e 29), al lo ws us ers t o pre d i c t r ab acc u ra t e ly . t h is fe a t ur e is va l u a b le fo r p r e c isio n, rh e o s t a t m o de , o r o p en-lo o p a pplica t ion s w h ere kn o w le dg e o f a b s o l u t e r e sis t an ce is cr i t ical . the s t o r e d t o ler a n c es r e side in t h e r e ad-o nl y mem o r y , a nd a r e exp r es s e d i n p e r c en t. th e t o lera n c e is co de d i n sig n ma g n i t ude bi n a r y , 1 6 bi t s l o n g , a n d i s s t ore d i n t w o m e m o r y l o c a t i on s ( s e e t a b l e 10). the da t a fo r m a t o f t h e t o lera n c e is t h e sig n ma g n i- t u de b i na r y fo r m a t an ex a m pl e is sh own in f i gur e 32. i n t h e f i r s t m e m o r y loca ti o n o f th e e i g h t d a ta b i t s , th e ms b i s desig n a t e d fo r t h e sig n (0 = a nd 1= ) an d t h e 7 ls bs a r e d e sign a t ed f o r th e in teg e r p o r t io n o f th e t o lera n c e . i n t h e s e c o nd me mor y l o c a t i o n , a l l e i g h t d a t a b i t s are d e s i g n a t e d for t h e d e cima l p o r t io n o f toler a n c e. a s sh own in t a b l e 8 an d f i gur e 32, f o r exa m p l e , if the ra ted r ab = 10 k? a nd t h e da t a r e ad back f r o m addr es s 11000 sh o w s 0001 1100 a nd addr es s 11001 s h o w s 00 00 1111, th en rd a c 0 t o leran c e ca n be calc u l a t ed as ms b 0 = n e xt 7 ms b 00 1 1100 = 28 8 ls b 0000 1111 = 15 2 8 = 0.06 t o leran c e = 2 8.06% and t h er e f o r e r ab_a ct u a l = 12.806 k? eemem write-acknowledg e polling af t e r e a ch wr i t e o p era t ion t o t h e eemem r e g i s t ers, a n in t e r n al wr i t e c y cle b e g i n s . th e i 2 c in t e r f ace o f t h e de vice is dis a b l e d . i n o r der t o det e r m ine if t h e in t e r n al wr i t e c y cle is co m p let e and th e i 2 c in ter f ace is ena b le d , in ter f ace p o l l in g c a n b e exe c u t e d . i 2 c in ter f ace p o l l in g can b e cond uc te d b y s e ndi n g a st a r t co ndi - t i o n fol l o w e d b y t h e sla v e addr es s t h e wr i t e b i t. i f t h e i 2 c in t e r f ace r e sp onds w i t h an a c , t h e wr i t e c y cle is co m p let e and t h e in t e r f ace is re ad y t o p r o c e e d wi t h f u r t h e r o p era t io n s . o t h e r - wis e , i 2 c in ter f ace p o l l in g c a n b e r e p e a t e d u n t i l i t succe e ds. c o mman d s 2 and 7 a l s o r e q u ir e ack n o w le dge p o l l in g. eemem write protection se t t i n g th e wp p i n t o a log i c l o w a f t e r eemem p r og ra mmin g prote c t s t h e me mor y an d r d a c re g i ste r s f r om f u tu re w r i t e o p er a t io ns. i n t h is m o de, t h e e e mem a nd r d a c r e ad o p era t io ns o p er a t e as n o r m al . w h en wr i t e p r o t e c t i o n is ena b le d , co mman d s 1 (r es t o r e f r o m eemem t o rd a c ) a nd 7 (r eset) f u n c tion n o r m a l l y t o al lo w rd a c s e t t in gs t o b e r e f r es h e d f r om t h e eemem t o t h e r d a c r e g i st ers.
ad5253/ad5254 rev. 0 | page 19 of 28 i 2 c c o mp a t ible 2- wire serial bus sd a frame 1 slave address byte frame 2 instruction byte scl ack. by ad525x ack. by ad525x ack. by ad525x frame 1 data byte stop by master 03824-0-013 start b y master 0 1 1 0 11 ad1 ad0 r/w x x x x x x x x d7 d6 d5 d4 d3 d2 d1 d0 91 9 1 9 f i g u re 33. gen e r a l i 2 c w r it e p a tt ern 03824-0-014 sda frame1 slave address byte frame 2 rdac register scl ack.by ad525x no ack.by master stop by master startby master 0 1 1 0 11 ad1 ad0 d7 d6 d5 d4 d3 d2 d1 d0 91 9 r/w f i g u re 34. gen e r a l i 2 c read p a tt ern the f i rs t b y t e o f th e ad5253/ad5254 is a s l a v e addr es s b y t e (s e e f i gur e 24 and f i gur e 25). i t has a 7- b i t sl a v e addr ess and an r/ w b i t. the 5 m s b o f th e sla v e addr es s a r e 0101 1, a n d t h e fol l o w in g 2 ls b a r e det e r m i n e d b y t h e s t a t es o f t h e ad1 and ad0 p i n s . ad1 a nd ad0 al lo w th e us er t o p l ac e u p t o f o ur ad5253/ad52 54s o n on e b u s. the 2-wir e i 2 c s e r i al b u s proto c o l op e r at e s a s f o l l ow s : ad5253/ad52 54 ca n be con t rol l ed via an i 2 c co m p a t i b le s e r i al b u s, a nd a r e co n n e c te d to t h is b u s as sla v e d e v i c e . the 2- wir e i 2 c s e r i al b u s p r o t o c ol f o l l o w s ( s ee f i gur e 33 and f i gur e 34): 1. the mas t er ini t i a t e s a da t a t r a n s f er b y es t a b l is hi n g a s t a r t co n d i ti o n , s u c h th a t s d a g o e s f r o m h i gh t o lo w wh ile sc l is hig h (f igur e 33). th e fol l o w i n g b y t e is t h e sl a v e addr es s b y te, w h ich co nsists o f t h e 5 m s b o f a sl a v e ad dr ess def i n e d as 01011. the next tw o b i ts a r e ad1 and ad0, i 2 c de vic e addr es s b i t s . d e p e ndi n g o n t h e s t a t es o f t h eir a d 1 an d ad0 b i ts, f o ur ad5253/ad52 54s ca n be addres s e d on t h e s a me b u s. th e l a s t ls b , th e r/ w b i t, det e r m i n es w h et her da ta is r e ad f r o m o r wr i t t e n t o th e sla v e device . the s l a v e w h os e addr es s co r r esp o n d s t o t h e t r an smi t t e d addr ess r e sp onds b y p u l l in g t h e s d a l i n e lo w d u r i n g t h e nin t h clo c k p u ls e (t his is ca l l e d a n ack n o w le dge b i t). a t t h i s s t a g e , al l o t h e r de v i ces o n t h e b u s r e ma in i d le w h i l e t h e s e l e c t e d d e v i c e w a i t s for da t a to b e w r it te n to or re a d f r om it s s e r i a l re g i s t e r . 2. i n t h e wr i t e m o de (excep t w h e n r e s t o r in g ee mem t o t h e rd a c r e g i st er), t h er e is an inst r u c t io n b y t e t h a t fol l o w s t h e s l a v e addr es s b y t e . th e ms b o f t h e i n s t r u c t io n b y t e lab e le d cmd/ reg . ms b = 1 ena b les cmd , t h e co mman d in st r u c t io n b y t e ; ms b = 0 ena b les gen e ra l r e g i ster wr i t ing. the t h ir d m s b i n t h e inst r u c t io n b y t e , lab e le d ee/ rd a c , i s tr ue o n l y wh en ms b = 0 o r in gen e ral wr i t in g m o de . ee ena b les t h e eemem r e g i s t er and reg enab les t h e r d a c r e g i s t er . the 5 l s b , a4 t o a0, desig n e d t h e addr es s e s o f t h e eemem a nd r d a c r e g i sters; s e e f i gur e 27 and f i gur e 28. w h en msb = 1 o r w h e n i n cm d mo de , t h e fo ur b i ts f o l l o w in g ms b a r e c3 t o c1, w h ic h co r r es p o nd t o 12 p r e d ef ine d ee mem co n t r o ls a nd q u ick co m m a nds; t h er e a r e als o f o ur fact o r y r e s e r v ed co mman d s. th e 3 ls ba2, a1, a nd a0 a r e 4-cha n nel rd a c addr ess e s (s e e f i gur e 31). af t e r ac kn o w ledg ing th e in s t r u c t io n b y t e , t h e las t b y te in the wr i t e mo de is t h e da ta b y t e . d a ta is tra n smi t t e d o v er th e s e r i al b u s in s e q u e n ces o f nin e c l o c k p u ls es (eig h t da t a b i ts fol l o w e d b y a n ack n o w le dg e b i t). th e tra n si ti o n s o n t h e s d a lin e m u s t occur d u ri n g th e lo w pe ri od o f s c l a n d r e m a in s t a b l e d u ri n g th e h i gh pe ri od o f scl (f igur e 33). 3. i n c u r r en t r e ad m o de , t h e rd a c 0 da t a b y t e imm e di a t e l y fol l o w s th e ac k n o w le dg m e n t o f th e sla v e addr ess b y t e . af t e r a n ack n o w le dge m e n t, r d a c 1 fol l o w s, t h en rd a c 2, a nd s o o n (t h e r e is a s l ig h t dif f er en ce i n wr i t e m o de , w h er e t h e l a s t eig h t da t a b i ts rep r es en t i n g rd a c 3 da t a a r e fol l o w e d b y a n o a c k n o w led g e b i t ) . s i m i la r l y , t h e tra n si ti o n s o n th e s d a l i ne m u st o c c u r d u r i ng t h e l o w p e r i o d of s c l a n d re m a i n s t a b le d u r i n g t h e hig h p e r i o d o f scl (s ee f i gure 34). a n ot he r re a d i n g me t h o d , r a n d om re a d me t h o d , i s s h ow n in f i gur e 30. 4. w h en all da ta b i t s ha v e been r e a d o r w r i t t e n , a s t o p co ndi t i on is est a b l ish e d b y t h e mast er . a st o p c o n d i t ion is def i n e d as a lo w-to -hig h t r a n s i t i o n o n t h e sd a l i ne w h i l e scl is hig h . i n wr i t e mo de , t h e mas t er p u l l s t h e s d a li ne hig h d u r i n g t h e 10 th clo c k p u ls e t o es t a b l ish a s t o p co ndi t i on (f igu r e 33). i n r e ad m o de , t h e master is s u es a n o ac kn o w le dg e f o r th e nin t h c l o c k p u ls e , i . e . , t h e s d a line r e ma in s hig h . th e mas t er t h e n b r in gs t h e s d a lin e lo w be f o r e th e 10 th clo c k p u ls e, w h ich go es hig h t o e s t a b l ish a st o p con d i t io n ( f igur e 34).
ad5253/ad5254 rev. 0 | page 20 of 28 theory of operation the ad5253/ad5254 are quad-channel digital potentiometers in 1 k?, 10 k?, 50 k?, or 100 k? that allow 64/256 linear resis- tance step adjustments. the ad5253/ad5254 employ double- gate cmos eeprom technology that allows resistance settings and user-defined data stored in the eemem registers. the eemem is nonvolatile such that settings remain when power is removed. the rdac wiper settings are restored from the nonvolatile memory settings during device power-up and can also be restored at any time during operation. the ad5253/ad5254 resistor wiper positions are determined by the rdac register contents. the rdac register acts like a scratch-pad register, allowing unlimited changes of resistance settings. rdac register contents can be changed using the devices serial i 2 c interface. the format of the data-words and the commands to program the rdac registers are discussed in the i 2 c interface section. the four rdac registers have corresponding eemem memory locations that provide nonvolatile storage of resistor wiper position settings. the ad5253/ad5254 provide commands to store the rdac register contents to their respective eemem memory locations. during subsequent power-on sequences, the rdac registers are automatically loaded with the stored value. whenever the eemem write operation is enabled, the device activates the internal charge pump and raises the eemem cell gate bias voltage to a high level; this essentially erases the current content in the eemem register and allows subsequent storage of the new content. saving data to an eemem register consumes about 35 ma of current and lasts approximately 26 ms. because of charge pump operation, all rdac channels may experience noise coupling during the eemem writing operation. the eemem restore time in power-up or during operation is about 300 s. note that the power-up eemem refresh time depends on how fast v dd reaches its final value. as a result, any supply voltage decoupling capacitors limit the eemem restore time during power-up. figure 20 shows the power-up profile where v dd , without any decoupling capacitors connected to it, is applied with a digital signal. the device initially resets the rdacs to midscale before restoring the eemem contents. in addition, users should issue a nop command 0 immediately after using command 1 to restore the eemem setting to rdac, thereby minimizing supply current dissipation. reading user data directly from eemem does not require a similar nop command execution. in addition to the movement of data between rdac registers and eemem memory, the ad5253/ad5254 provide other shortcut commands that facilitate the users programming needs, as shown in table 11. table 11. ad5253/ad5254 quick commands commmand description 0 nop. 1 restore eemem content to rdac. user should issue nop immediately after this command to conserve power. 2 store rdac register setting to eemem. 3 decrement rdac 6 db (shift data bits right). 4 decrement all rdacs 6 db (shift all data bits right). 5 decrement rdac one step. 6 decrement all rdacs one step. 7 reset eemem contents to all rdacs. 8 increment rdac 6 db (shift data bits left). 9 increment all rdacs 6 db (shift all data bits left). 10 increment rdac one step. 11 increment all rdacs one step. 12C15 reserved. linear increment and decrement commands the increment and decrement commands (#10, #11, #5, #6) are useful for linear step adjustment applications. these commands simplify microcontroller software coding by allowing the controller to send just an increment or decrement command to the ad5253/ad5254. the adjustments can be directed to a single rdac or to all four rdacs. 6 db adjustments (doubling/halving wiper setting) the ad5253/ad5254 accommodate 6 db adjustments of the rdac wiper positions by shifting the register contents to left/ right for increment/decrement operations, respectively. com- mands 3, 4, 8, and 9 can be used to increment or decrement the wiper positions in 6 db steps synchronously or asynchronously. incrementing the wiper position by +6 db is essentially doubling the rdac register value, while decrementing by C6 db is halving the register content. internally, the ad5253/ad5254 use shift registers to shift the bits left and right to achieve a 6 db increment or decrement. the maximum number of adjustments is nine and eight steps for increment from zero scale and decrement from full scale, respectively. these functions are useful for various audio/video level adjustments, especially white led brightness settings where the visual responses of humans are more sensitive to large rather small adjustments.
ad5253/ad5254 rev. 0 | page 21 of 28 digit a l input/output c o nfigur a t ion s d a i s a d i g i tal i n p u t / o u t p u t wi th a n o p e n - d ra in m o s f et th a t r e q u ir es a p u l l - u p r e sis t o r fo r p r o p er co mm uni c a t ion. on t h e o t h e r hand , sc l a nd wp are d i g i t a l i n pu t s w i t h pu l l - u p r e sisto r s r e co mm e n d e d to mini mi ze t h e mos f et cr o s s- co n d ucti o n w h en th e d r i v i n g sign als a r e lo w e r th a n v dd . s c l a nd wp ha ve es d p r o t e c t i o n dio d es, as sh own i n f i gur e 35 a nd f i gur e 36. wp ca n be pe rm a n e n tl y ti ed t o v dd w i t h out a pu l l - u p re s i stor i f t h e wr i t e-p r o t e c t fe a t ur e is n o t us e d . i f wp is lef t f l o a t i n g , an in t e r n al c u r r en t s o ur ce wil l p u l l i t lo w t o ena b le wr i t e-p r o t ec t. i n a p plic a t io n s w h er e t h e d e vi c e is n o t b e in g p r og ra mm e d o n a f r eq ue n t ba s i s , t h i s all o w s th e pa r t t o d e fa ul t t o w r i t e- p r o t ec t af te r a n y one - t i me f a c t or y pro g r a m m i ng or f i el d c a l i br a t i o n w i t h out u s i n g a n on - b o a rd pu l l - d ow n re s i stor . si nc e t h e r e are prote c t i on d i o d e s on a l l t h e s e i n put s , t h e i r s i g n a l l e vel s m u s t n o t be gr ea t e r th a n v dd t o p r ev en t f o r w a r d b i a s i n g o f th e d i o d e s . 03824-0-035 gnd s cl v dd f i g u re 35. scl d i g i t a l i n put 03824-0-036 gnd inputs wp v dd f i g u re 36. equiv a le nt wp di gi ta l i n p u t mul t iple de vices on one bus ad5253/ad52 54 a r e eq ui p p e d wi t h tw o addr es sin g p i n s , ad1 a nd ad0, tha t a l lo w u p t o f o ur ad5253/ad52 54s t o be o p er a t e d on one i 2 c b u s. t o achie v e t h i s r e su l t , t h e st a t es o f ad1 and a d 0 o n e a ch de vic e m u st f i rst b e def i n e d . an ex am pl e is s h own in t a b l e 12 a nd f i gur e 37. i n i 2 c p r o g ra mmi n g , e a ch de vice is iss u ed a dif f er en t sla v e addr es s0101 1(ad1)(ad0) to co m p lete t h e addr essing. tab l e 12. multip le dev i ces a d d r essin g a d 1 a d 0 device addr es s e d 0 0 u 1 0 1 u 2 1 0 u 3 1 1 u 4 03824-0-037 v dd r p r p +5v v dd v dd u1 ad0 ad1 sda scl master u2 ad0 ad1 sda scl u3 ad0 ad1 sda scl u4 ad0 ad1 sda sda scl scl f i g u re 37. m u lt ip le a d 52 53 /a d5 2 54s on a s i ng l e bus i n wirel e ss b a s e st a t ion s m ar t an te nna s y ste m s w h e r e ar r a y s of di g i t a l p o te n t i o me te rs ma y b e ne e d e d to bi a s t h e p o we r a m p l if iers, la rg e n u m b ers o f ad5253/ad5254s ca n be addr ess e d b y usin g ex t r a de co d e rs, swi t ch es, a nd i/o b u s e s, as show n i n f i g u re 3 8 . f o r e x am ple, to c o mm u n i c a t e to a tot a l of 16 de vices, fo ur de co ders and 1 6 s e ts o f co m b i n a t io na l sw i t ches ( f ou r s e t s show n i n fi g u re 3 6 ) are ne e d e d . t w o i / o bu s e s s e r v e as the co mm on in p u ts o f th e f o ur 2 4 deco ders a n d s e lec t f o u r s e ts o f o u t p u t s a t eac h com b ina t io n. b e c a us e t h e f o ur s e ts o f co m b in a t ion s w i t ch ou t p u t s a r e uniq ue , as sh o w n in f i gur e 38, a sp e c if ic d e vice i s addr ess e d b y p r o p er i 2 c p r o g ra mmin g w i t h th e sla v e addr ess def i ned as 01011(ad1)(ad0). this o p er a t io n a l l o w s one out of 1 6 d e v i c e s to b e a d d r e s s e d, pr ov i d e d t h e in p u ts o f t h e two de co ders do no t cha n ge st a t es. the de co ders in p u ts a r e al lo w e d t o cha n ge once t h e op era t io n o f t h e s p e c if ie d de vice is com p l e te d .
ad5253/ad5254 rev. 0 | page 22 of 28 03824-0-038 +5v r1 ad1 ad0 n1 4 2 4 +5v r2 x ad1 ad0 n2 x +5 p2 y p2 y p3 x r3 x r3 y n3 y ad1 ad0 ad1 ad0 4 4 4 +5v p4 r4 +5v 2 4 decoder 4 2 4 decoder 4 2 4 decoder 4 2 4 decoder f i g u re 38. f o u r d e v i c e s w i t h a d 1 and a d 0 of 0 0 terminal vol t a g e o p e r a t ion r a nge the ad5253/ad5254 a r e desig n e d wi t h in t e r n al es d dio d es fo r p r o t e c t i o n ; t h es e dio d es als o s e t t h e b o u ndar y o f t h e t e r m inal o p er a t in g v o l t a g es. p o si ti v e sig n als p r es en t on t e r m inal a , b , o r w th a t e x ceed v dd are cl am p e d b y t h e for w ard b i a s e d dio d e . s i mil a rl y , n e g a ti ve sig n als o n t e r m inal a, b , o r w tha t a r e m o r e n e ga ti v e th a n v ss are a l s o cl am p e d ( s e e f i g u re 3 9 ) . i n p r ac t i ce , us ers s h o u ld n o t op era t e v ab , v wa , a n d v wb to b e hig h er t h a n t h e v o l t a g e acr o s s v dd -t o-v ss , b u t v ab , v wa , a nd v wb h a ve no p o l a r i t y c o nst r ai n t . 03824-0-039 v dd a w b v ss f i g u re 39. m a x i mu m t e r m i n a l v o lt ag es s e t by v dd and v ss po wer-up and po wer-do wn sequences sin c e t h e es d pr o t e c t i o n di o d e s limi t t h e v o l t ag e co m p l i an ce a t t e r m ina l s a, b , a nd w (f igur e 39), i t is im p o r t a n t t o p o w e r v dd /v ss bef o r e a p p l yin g an y v o l t a g e t o t e r m ina l s a, b , a nd w . o t h e r w is e , t h e dio d es a r e fo r w a r d- b i as e d s u ch t h a t v dd /v ss ar e p o w e r e d uni n te n t io na l l y an d m a y a f fe c t t h e r e st o f t h e us er s cir c ui t. s i mi la rly , v dd /v ss s h o u ld be po w e r e d do w n la s t . th e ide a l p o w e r - u p s e q u e n ce is i n t h e fol l o w in g o r der : gnd , v dd , v ss , dig i t a l in puts, a nd v a /v b /v w . t h e ord e r of p o we r i ng v a , v b , v w , a nd t h e dig i t a l in pu ts is n o t im p o r t an t, as lon g as t h e y a r e po w e r e d a f t e r v dd /v ss . l a y o ut an d power s u ppl y biasi n g i t is a l wa y s a go o d p r ac t i ce t o em plo y a co m p a c t, mini m u m le ad-len gt h l a yo u t desig n . the le ads t o t h e in p u t s h o u l d b e as dir e c t as p o ssi b l e , wi t h a mini m u m con d uc to r l e n g t h . gr o u nd p a th s sh o u ld ha v e lo w r e sis t a n c e a nd lo w in d u c t a n ce . s i mil a rl y , i t is al s o g o o d p r ac tic e t o b y p a s s the p o w e r s u p p lies wi t h q u ali t y ca p a ci t o rs. l o w es r (eq u i v alen t s e r i es r e sis t a n ce) 1 f t o 10 f ta n t al u m o r e l ec tr ol ytic ca p a ci t o rs s h o u ld be a p plie d a t t h e su p p lies t o minimize an y t r a n si en t di s t urb a n c e a n d fi l t e r l o w fr e q u e n c y r i p p l e . f i g u r e 4 0 i l l u s t r a t e s th e ba s i c s u p p l y -b yp as sing co nf igura t io n f o r th e ad5253 /ad5254. 03824-0-040 v dd v dd v ss v ss gnd c3 ad5253/ad5254 c4 c1 c2 10 f 10 f 0.1 f 0.1 f f i g u r e 4 0 . p o w e r su pp l y by pa s s i n g the g r o u nd p i n o f th e ad5253/ad5254 is us ed p r ima r il y as a dig i t a l g r o u nd r e fer e n c e. t o mi nimi ze t h e dig i t a l g r o u n d bo u n ce , t h e ad5253/ad5254 g r o u n d ter m inal s h o u ld b e jo in e d re mot e ly to t h e c o m m on g r ou n d ( s e e f i g u re 4 0 ) .
ad5253/ad5254 rev. 0 | page 23 of 28 digit a l po tent iome t e r oper a t i o n the s t r u c t ur e of t h e rd a c is desig n e d t o em u l a t e t h e p e r f or m a nc e of a m e ch an i c a l p o te n t i o me te r . t h e r d a c c o n t ai ns a st r i n g of re s i stor s e g m e n t s , w i t h an ar r a y of an a l o g sw i t ch es ac t i n g as t h e w i p e r conn e c t i o n t o t h e r e sis t o r a r ra y . the n u m b er o f p o in ts is t h e r e s o l u t i o n o f t h e de v i ce . f o r exa m p l e , th e ad5253/ad5254 em u l a t es 64/25 6 co nnec t io n p o in ts wi t h 64/256 eq ual r e sis t a n c e , r s , al lo win g i t t o p r o v ide bet t er than 1.5 % /0.4 % s e t t ab il i t y r e s o l u tio n . f i gur e 41 p r o v ides a n eq ui v a l e n t dia g ra m o f th e co n n ect i o n s bet w ee n t h e th r e e t e r m inals t h a t mak e u p on e cha nne l o f t h e rd a c . s w i t ch es sw a an d s w b a r e al wa ys o n , w h i l e on e o f s w i t ch es s w (0) t o sw(2 nC 1 ) i s on one a t a t i me, d e p e nd i n g on t h e s e tt i n g d e c o d e d f r o m t h e da t a b i t. since t h e s w i t ch es a r e n o ni de al , t h er e is a 75 ? wi p e r r e sis t a n ce , r w . w i p e r r e s i s t a n c e i s a f u n c t i o n o f su p p ly vol t age and te m p e r a t u r e ; l o we r su p p ly v o l t age s and hig h er t e m p era t ur es r e s u l t in hi g h er wi p e r r e sis t a n ces. c o n s idera t ion of wi p e r r e sist a n ce d y namics is i m p o r t a n t i n a p plic a t ion s w h er e acc u ra t e p r e d ic t i o n o f o u t p u t r e sist an ce is re qu i r e d . 03824-0-041 sw a a x sw (2 n ? 1) sw (2 n ? 2) sw(1) digital circuitry omiitted for clarity rdac wiper register and decoder sw(0) sw b r s = r ab /2 n b x w x r s r s r s f i gure 41. equiv a le nt r d a c struc t ure progr a mm able rheost a t oper a t ion i f ei t h er t h e w - to-b o r w - t o - a ter m inal is us e d as a va r i ab le re s i stor , t h e u n u s e d te r m i n a l c a n b e op e n e d or shor te d w i t h w ; s u c h o p e r a t i o n is call ed rh eos t a t m o de (see f i gur e 42). t h e r e sis t a n c e t o lera n c e can ra n g e 20%. 03824-0-042 a b w a b w a b w f i g u re 42. r h e o s t at m o de conf ig ur at i o n the n o minal r e sis t a n ce o f the ad5253/ad52 54 has 64/256 co n t ac t p o i n ts a c cess e d b y t h e wi p e r t e r m ina l , pl us t h e b t e r m inal co n t ac t. th e 6- /8- b i t da t a -w o r d in t h e rd a c r e g i st er is deco de d t o s e lec t o n e o f t h e 6 4 /256 s e t t in gs. the wi p e r s f i rs t co nne c t io n st a r ts a t t h e b ter m i n a l fo r da t a 0x 0 0 . this b ter m i- na l co n n e c t i on has a wi p e r co n t ac t r e sist an ce, r w , o f 75 ?, re g a rd l e ss of t h e no m i n a l re s i st anc e . t h e s e c o n d c o n n e c t i o n (ad5253 10 k? p a r t ) is th e f i rs t ta p p o in t w h er e r wb = 231 ? [r wb =r ab /64 + r w = 156 ? + 75 ?] f o r da ta 0x 01, a n d s o o n . e a c h l s b da ta val u e in cr ea se m o v e s th e wi pe r u p th e r e si s t o r ladder un til t h e las t t a p p o in t is r e ac h e d a t r wb = 9893 ?. s e e f i gur e 41 f o r a sim p lif i e d dia g ram o f th e e q ui va len t rd a c cir c ui t. t h e g e n e ral eq ua ti o n tha t d e t e r m in e s th e d i g i ta ll y p r ogra m m ed o u t p u t r e s i s t a n ce bet w een w a n d b , i s r wb ( d ) = ( d /64) r ab + 75 ? ( ad52 53 ) ( 1 ) r wb ( d ) = ( d /256) r ab + 75 ? ( ad52 54 ) ( 2 ) w h er e d is t h e de cima l e q ui va l e n t d a t a con t ai ne d i n t h e rd a c la t c h, an d r ab is t h e n o m i na l e nd-to - e n d r e sist an ce. (%) d (code in decimal) 03824-0-043 0 25 50 75 100 0 10 32 48 63 r wa r wb f i gur e 4 3 . ad52 53 r wa (d) and r wb (d) vs . d ecimal c o d e
ad5253/ad5254 rev. 0 | page 24 of 28 for example, the r wb values shown in table 13 can be found on ad5253 10 k? parts. table 13. r wb vs. codes; r ab = 10 k?, a terminal = open d (dec) r wb (?) output state 63 9918 full scale 32 5075 midscale 1 231 1 lsb 0 75 zero scale (wiper resistance) note that in the zero-scale condition, a 75 ? finite wiper resistance is present. care should be taken to limit the current conduction between w and b in this state to no more than 5 ma continuous for a total resistance of 1 k?, or a 20 ma pulse, to avoid degradation or possible destruction of the internal switch contact. similar to the mechanical potentiometer, the resistance of the rdac between wiper w and terminal a also produces a digitally controlled complementary resistance, r wa . when these terminals are used, the b terminal can be opened. setting the resistance value for r wa starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value (see figure 41). the general equation for this operation is r wa ( d ) = [(64 C d )/64] r ab + 75 ? ( ad5253 ) (3) r wa ( d ) = [(256 C d )/256] r ab + 75 ? ( ad5254 ) (4) table 14. r wa vs. codes; ad5253, r ab = 10 k?, b terminal = open d (dec) r wa (?) output state 63 231 full-scale 32 5075 midscale 1 9918 1 lsb 0 10075 zero-scale the typical distribution of r ab from channel-to-channel matches is about 0.15% within a given device. on the other hand, device-to-device matching is process lot dependent with a 20% tolerance. programmable potentiometer operation if all three terminals are used, the operation is called potenti- ometer mode and the most common configuration is the voltage divider operation (see figure 44). 03824-0-044 a b w v i v c figure 44. potentiometer mode configuration if the wiper resistance is ignored, the transfer function is simply b ab w v v d v + = 64 ( ad5253 ) (5) b ab w v v d v + = 256 ( ad5254 ) (6) a more accurate calculation, which includes the wiper resistance effect, yields a w ab w ab n w v r r r r d d v 2 2 ) ( + + = (7) where 2 n is the number of steps. unlike in rheostat mode operation where the tolerance is high, potentiometer mode operation yields an almost ratiometric function of d /2 n with a relatively small error contributed by the r w terms. therefore, the tolerance effect is almost cancelled. similarly, the ratiometric adjustment also reduces the temperature coefficient effect to 50 ppm/c, except at low value codes where r w dominates. potentiometer mode operations include other applications such as op amp input, feedback resistor networks, and other voltage scaling applications. the a, w, and b terminals can in fact be input or output terminals, provided |v a |, |v w |, and |v b | do not exceed v dd -to-v ss .
ad5253/ad5254 rev. 0 | page 25 of 28 appli c a t ions rgb led l c d ba c k ligh t c o ntrol l er h i gh po w e r (> 1 w ) r g b l e d s h a v e been im p r o v ed so d r a m a t ical l y in ef f i cien c y a n d c o s t tha t t h ey a r e lik e l y t o r e p l ac e ccfls (co l d c a t h o d e f l o r es cen t la m p s) as backlig h tin g s o ur ces in hig h en d l c d p a n e ls in t h e n e a r f u t u r e . u n l i k e co n v en tio n a l led s , hig h p o w e r led s ha v e a fo r w a r d v o l t a g e o f 2 v t o 4 v , a n d co ns um e m o r e tha n 350 ma a t maxim u m b r ig h t n e s s . the l e d br i g h t ne ss i s a l i ne ar f u nc t i on of t h e c o n d u c t i on c u r r e n t b u t n o t t h e fo r w a r d v o l t a g e . t o in cr e a s e b r ig h t n e s s o f a g i v e n co lo r , m u l t i p le led s can be co nn ec t e d in s e r i es, ra th er than in p a ral l e l , t o achie v e unifo r m b r ig h t n e ss. f o r exa m ple , t h r e e r e d led s co nf igur e d in s e r i es r e q u i r e a n a v era g e o f 6 v t o 12 v v o l t a g e h e adr o o m , b u t t h e cir c ui t o p er a t io n r e quir es c u r r en t c o n t ro l. a s a re s u lt , f i g u re 4 5 sh ow s t h e i m pl e m e n t a t i on of o n e h i gh po w e r r g b l e d c o n t r o ll e r u s i n g a d i gi tal po t e n t i o m e t e r ad5254, a bo ost r e gu la t o r , a n op a m p , an d p o w e r m o s f et s. the ad p1610 ( u 2 in f i gur e 45) is a n ad j u s t a b l e bo os t regu la t o r wi t h i t s o u t p u t ad j u s t e d b y the ad5254 s rd a c 3. s u c h a n output s h ou l d b e s e t h i g h e n ou g h f o r prop e r op e r a t i o n but l o w en o u g h t o co n s er v e p o w e r . th e ad p1610 s 1.2 v ban d g a p r e fer e n c e is b u f f er e d t o p r o v ide t h e r e fer e n c e le v e l fo r t h e v o l t a g e dividers s e t b y th e ad5 254 s rd a c 0 t o rd a c 2 and r e sis t o r s r2 t o r4. f o r exa m p l e , b y ad j u s t in g t h e ad5254 s rd a c 0, t h e des i ra b l e v o l t a g e a p p e a r s acr o ss t h e s e n s e r e sist o r s, r r . i f u 2 s output i s s e t prop e r l y , op am p u 3 a an d p o we r m o s f et n 1 do wha t ev er is n e ces s a r y t o r e gula t e t h e c u r r en t o f t h e lo o p . a s a r e su l t , t h e c u r r en t t h r o ug h t h e s e n s e r e sist o r an d th e r e d l e d s i s r rr r r v i = ( 8 ) r 8 i s n e ed e d t o p r ev e n t oscilla t io n . i n addi tion t o t h e 256 l e v e ls o f ad j u s t ab le c u r r en t/b r ig h t n e s s , user s m a y also a p p l y a pw m sig n al a t u 3 s sd pi n t o a c h i e v e fi n e r b r i g h t n e s s r e s o l u t i o n o r be t t e r p o w e r e ffi c i e n c y .
ad5253/ad5254 rev. 0 | page 26 of 28 03824-0-045 ad8594 u3b u3a ad8594 +5v c10 u3d scl sda r4 r3 r2 c1 22k ? 22k ? 250k ? 250k ? 10k ? 10k ? 10k ? 250k ? 10k ? 10k ? 10k ? 4.7 ? 0.1 ? 4.7 ? 0.1 ? 4.7 ? 0.1 ? 100k ? 10 f 390 f 0.1 f 10 f 10 f r7 r6 a3 u1 rd ac3 clk sdi a2 b2 a1 b1 rdac2 rdac1 a0 l1 - slf6025-100m1r0 d1 - mbr0520lt1 w0 pwm w1 w2 b0 rdac0 gn d a d 0 a d 1 ad5254 b3 r c r1 r5 u2 d1 db1 db2 db3 dg1 dg2 dg3 dr1 v out dr2 dr3 vb n3 ib ig ir vg vrb n2 c3 r10 rb r9 r8 vrr irfl3103 i r f l 3103 ir fl3 1 0 3 vr rr rg vrg n1 +5v c11 8 u3c 4 l1 v dd c ss c c v ss v ref = 2.5v 10 f 0.1 f ad8594 ad8594 sd v+ v? adp1610 in sw fb comp ss rt gnd sd f i g u re 45. d i g i t a l p o tent io me te r - b a se d r g b led c o ntroller
ad5253/ad5254 rev. 0 | page 27 of 28 outline dimensions 20 1 11 10 6.40 bsc 4.50 4.40 4.30 pin 1 6.60 6.50 6.40 seating plane 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 compliant to jedec standards mo-153ac coplanarity 0.10 f i gure 46. 2 0 -l ead thin shr i nk s m a l l o u tline p a ckage [ t ssop ] (ru - 20) di me nsio ns sho w n i n mi ll im e t e r s ordering guide m o d e l s t e p r ab (k?) temperature r a nge package descri ption package option full container quantity ad5253bru1 64 1 ?40c to +85c thin shrink small outline package (tssop) ru-20 75 ad5253bru1-rl7 64 1 ?40c to +85c thin shrink small outline package (tssop) ru-20 1,000 ad5253bru10 64 10 ?40c to +85c thin shrink small outline package (tssop) ru-20 75 ad5253bru10- rl7 64 10 ?40c to +85c thin shrink small outline package (tssop) ru-20 1,000 ad5253bru50 64 50 ?40c to +85c thin shrink small outline package (tssop) ru-20 75 ad5253bru50- rl7 64 50 ?40c to +85c thin shrink small outline package (tssop) ru-20 1,000 ad5253bru100 64 100 ?40c to +85c thin shrink small outline package (tssop) ru-20 75 ad5253bru100 -rl7 64 100 ?40c to +85c thin shri nk small outline package (tssop) ru-20 1,000 a d 5 2 5 3 e v a l 6 4 1 0 e v a l u a t i o n boar d 1 ad5254bru1 256 1 ?40c to +85c thin shrink small outline package (tssop) ru-20 75 ad5254bru1-rl7 256 1 ?40c to +85c thin shrink small outline package (tssop) ru-20 1,000 ad5254bru10 256 10 ?40c to +85c thin shrink small outline package (tssop) ru-20 75 ad5254bru10- rl7 256 10 ?40c to +85c thin shrink small outline package (tssop) ru-20 1,000 ad5254bru50 256 50 ?40c to +85c thin shrink small outline package (tssop) ru-20 75 ad5254bru50- rl7 256 50 ?40c to +85c thin shrink small outline package (tssop) ru-20 1,000 ad5254bru100 256 100 ?40c to +85c thin shrink small outline package (tssop) ru-20 75 ad5254bru100 -rl7 256 100 ?40c to +85c thin shri nk small outline package (tssop) ru-20 1,000 a d 5 2 5 4 e v a l 2 5 6 1 0 e v a l u a t i o n boar d 1
ad5253/ad5254 rev. 0 | page 28 of 28 notes purch a se of li c e n s e d i 2 c com p on en t s o f an a l og d e vi ces or on e of i t s subli c en s e d as soci a t ed c o m p a n i e s con v eys a li cen s e for t h e purch a ser un der t h e ph i li p s i 2 c p a te nt rights to us e the s e co mpo n e nts in an i 2 c sy st em , provi d e d t h a t t h e syst em c o n f orm s t o t h e i 2 c stand a rd speci f ication as d e f i ned by phil ips . ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . d03824C0C 4/04(0)

▲Up To Search▲

Price & Availability of AD5254BRU10-RL7

	To Download AD5254BRU10-RL7 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .